Latch registers are circuits that provide for the storage and transfer of data in digital form. Latch registers may be used to perform any one of several functions in a system, such as serving as control registers for controlling bus functions on a gate array. When programmable latch registers are used in a larger circuit, typically they are addressable so that the contents may be written and read and are therefore readily testable. However, this requires a substantial amount of additional circuitry that consumes valuable space on the silicon chip. Conventional, readable latch registers would require either multiplexers coupled to each register for interpreting the data or tri-state buffers coupled between the registers and a bus.
Therefore, if space on the silicon chip is limited, one typical option is to use non-readable latch registers in order to eliminate this additional circuitry used to test the latch registers. This is especially the case for control registers that are set only one time during power on reset and system initialization.
However, it would still be advantageous to be able to test the functionality of the non-readable registers, whether programmed only during power on reset or reprogrammed during use.
Thus, what is needed is a monolithically integrated circuit that provides for the testing of latch registers even though the registers are not directly readable.